This reverts commit ed63e949.

Do not treat warnings as errors when building flashrom. This fixes build failure with newer versions of GCC.

Coreboot is enabling PECI on these CPUs which, according to Intel erratum, must
only be done after loading microcode updates, otherwise the CPUID feature set
becomes corrupted. That's my understanding, and I think this is why SpeedStep
is broken. To be specific, it could but but operating systems no longer detect
that the feature is supported. In any case, belgin on IRC found the commit in
coreboot, after a bisect, enabling PECI. This commit in Libreboot adds a patch,
reverting coreboot's PECI patch.

just set it to the default, instead

or was used, instead of and

tianocore is a liability for the libreboot project. it's a bloated mess, and
unreliable, broken on many boards, and basically impossible to audit.

i don't trust tianocore, so i'm removing it.

the static site generator was forked into https://untitled.vimuser.org/

works around a build error with gcc 7.5. the patches being removed
from memtest86+ aren't really necessary for the average user anyway

you must de-solder the default chip and install the new one.
winbond w25q128fvsig is a nice choice of 16MB (128Mbit) IC

it is superior

This reverts commit 84a1bc50.

4mb and 8mb users can just pad their roms to 16mb, using the instructions on
<https://libreboot.org/faq.html#how-do-i-pad-a-rom-before-flashing>

maintaining them in lbmk is a waste of time, and also a hazard because it's a
lot of duplicated labour when making any changes, which could result in awful
mistakes being made